The present invention relates generally to an integrated circuit assembly with a bar bond connector. More specifically, the present invention relates to an integrated circuit assembly with a bar bond connector and improved soldered connections.
The present invention relates to a method and apparatus for electrically connecting an integrated circuit device, particularly a power transistor to a substrate. Field effect transistor (FET) devices are typically configured and packaged in arrangements (such as TO-220 or D-Pak type IC packages) in which the integrated circuit (IC) is mounted to a copper slug, wirebonded, and overmolded. The packaged assembly is then commonly mounted to a substrate by either thru hole or surface mount soldering processes. Although these xe2x80x9cpackagedxe2x80x9d IC devices have been widely known and utilized, it is also known that they can result in increased circuit board area and product costs. Trends for decreased circuit board area and reduced product costs within the electronics industry have therefore created a move to xe2x80x9cdepackagexe2x80x9d these devices. xe2x80x9cDepackagingxe2x80x9d these devices commonly consists of mounting the bare chip directly to the substrate. Although mounting the bare chip directly to the substrate can assist in the reduction of circuit board area and product costs, present methods of attaching the active circuit side of the chip to connection points on the substrate can have disadvantages.
One such known method utilizes wire bonding to connect the active circuit side of the chip to bond pads on the substrate. There can be several disadvantages to using wire bonding to make the electric connection from the FET device to the substrate. Many applications requiring the use of FET devices are high power and high current applications. The FET devices in these applications can drive high current loads, and therefore may require multiple wire bonds to be made to the chip. It is known that in some applications, as many as 10 aluminum wire bonds are needed to handle the current flow. The necessity of multiple wire bonds can result on a negative impact on product costs. In addition, because of the large number of wire bonds per device, it is known that device yield can be as low as 98%. In applications having numerous FET devices, this can have a negative impact on the overall system package yield. These undesirable consequences are often the result of the use of multiple wire bonds.
An additional undesirable consequence stemming from the use of wire bonding results from drain to source resistance (RDS). RDS (on) is a key parameter used to size the FET devices for a given application. RDS on often determines how large the device is and hence the cost.
As the number of wire bonds is increased, the amount of silicon area needed to bond out the device is increased, thereby driving the size of the device up. A method of reducing RDS is compared to wire bond technology in addition to increasing die size and reducing cost would be highly desirable. An alternate technology to wire bonding would therefore be preferable.
It is, therefore, an object of the present invention to provide an integrated circuit assembly with reduced dies, reduced RDS, increased current flow capacity and reduced costs. It is a further object of the present invention to provide an integrated circuit assembly with an improved connection between the IC device and the substrate.
In accordance with the objects of the present invention, an integrated circuit assembly is provided. The integrated circuit assembly includes a substrate having a substrate pad and an IC device having an IC pad. The IC device is mounted directly to the substrate. The present invention further includes a conductive bar element having a first and a second end. The first end is soldered to the IC pad and the second bar end is soldered to the substrate pad.
Other objects and features of the present invention will become apparent when viewed in light of the detailed description of the preferred embodiment when taken in conjunction with the attached drawings and appended claims.
FIG. 1 is a top view illustration of an embodiment of an integrated circuit assembly in accordance with the present invention;
FIG. 2 is a side view of the integrated circuit assembly illustrated in FIG. 1, the side view taken along lines 2xe2x80x942 in the direction of the arrows;
FIG. 3 is a top view illustration of an embodiment of an integrated circuit assembly in accordance with the present invention; and
FIG. 4 is a side vie of the integrated circuit assembly illustrated in FIG. 3, the side view taken along lines 3xe2x80x943 in the direction of the arrows.